Cache Refill/Access Decoupling for Vector Machines Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanović Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology

Source URL: www.lcs.mit.edu

• Computing
• Parallel computing
• Computer architecture
• Central processing unit
• Computer hardware
• Data parallelism
• Cache control instruction

MonetDB/X100: Hyper-Pipelining Query Execution Peter Boncz, Marcin Zukowski, Niels Nes CWI Kruislaan 413 Amsterdam, The Netherlands {P.Boncz,M.Zukowski,N.Nes}@cwi.nl

Source URL: www-db.cs.wisc.edu

• Central processing unit
• Relational database management systems
• Instruction set architectures
• Cross-platform software
• MonetDB
• Structured storage
• Column-oriented DBMS
• Pipeline
• CPU cache
• Optimizing compiler
• Vector processor
• Reduced instruction set computing

Efficient Software Implementation of Binary Field Arithmetic Using Vector Instruction Sets Diego F. Aranha Department of Computer Science University of Bras´ılia Joint work with

Source URL: caramba.loria.fr

• Computer architecture
• Computing
• X86 instructions
• Binary arithmetic
• Computer engineering
• Central processing unit
• Computer arithmetic
• Instruction set
• Streaming SIMD Extensions
• Bitwise operation
• Bit manipulation
• SSSE3

Procedure Call Standard for the ARM Architecture

Source URL: infocenter.arm.com

• Subroutines
• Central processing unit
• Acorn Computers
• ARM architecture
• Calling convention
• Application binary interface
• Pointer
• 64-bit computing
• Processor register
• Stack
• SIMD
• Instruction set

Modular Deductive Verification of Multiprocessor Hardware Designs Muralidaran Vijayaraghavan1 , Adam Chlipala1 , Arvind1 , and Nirav Dave2 1 MIT {vmurali,adamc,arvind}@csail.mit.edu

Source URL: plv.csail.mit.edu

• Computing
• Computer architecture
• Computer hardware
• Microprocessors
• Central processing unit
• IBM PC compatibles
• Instruction set architectures
• Microcomputers
• Program counter
• X86

Fast Binary Translation: Translation Efficiency and Runtime Efficiency Mathias Payer and Thomas R. Gross Department of Computer Science ETH Zürich

Source URL: hexhive.github.io

• Computer performance
• Software optimization
• Central processing unit
• Arrays
• Compiler optimizations
• Binary translation
• Lookup table
• Subroutine
• Instruction set
• Inline expansion
• Cache

Transformer: A Functional-Driven Cycle-Accurate Multicore Simulator Zhenman Fang1,2 , Qinghao Min2 , Keyong Zhou2 , Yi Lu2 , Yibin Hu2 , Weihua Zhang2 , Haibo Chen3 , Jian Li4 , Binyu Zang2 1 The State Key Lab of ASIC &

Source URL: ipads.se.sjtu.edu.cn

• Parallel computing
• Central processing unit
• Computer architecture
• Instruction set architectures
• Microprocessors
• CPU cache
• Computer architecture simulator
• ARM architecture
• Multi-core processor
• Speedup
• Emulator
• Microcode

Everybody be cool, this is a roppery! Vincenzo Iozzo zynamics GmbH Tim Kornau zynamics GmbH

Source URL: www.trailofbits.com

• Computing
• Computer architecture
• Computer engineering
• Central processing unit
• Return-oriented programming
• Instruction set
• Processor register
• Machine code
• Reduced instruction set computing
• Gadget
• Subroutine
• Stack machine

The design of the control circuit for an asynchronous instruction prefetch unit using signal transition graphs S.-H. Chung and S.B. Furber Department of Computer Science, The University of Manchester, Oxford Road, Manche

Source URL: apt.cs.manchester.ac.uk

Micro-Policies: Formally Verified Tagging Schemes for Safety and Security (Extended Abstract) C˘at˘alin Hrit¸cu (INRIA Paris)1 Today’s computer systems are distressingly insecure. A host of vulnerabilities arise fro

Source URL: software.imdea.org

• Computing
• Central processing unit
• Computer architecture
• Computer engineering
• Cache
• Instruction set
• Opcode
• Program counter
• Computer
• Tag
• CPU cache